By Vladislav Vashchenko,Mirko Scholz
This booklet addresses key facets of analog built-in circuits and structures layout regarding method point electrostatic discharge (ESD) protection. it truly is a useful reference for an individual constructing systems-on-chip (SoC) and systems-on-package (SoP), built-in with system-level ESD defense. The publication specializes in either the layout of semiconductor built-in circuit (IC) elements with embedded, on-chip process point safeguard and IC-system co-design. The readers may be enabled to convey the process point ESD safeguard options to the extent of built-in circuits, thereby lowering or thoroughly removing the necessity for added, discrete elements at the published circuit board (PCB) and assembly system-level ESD standards. The authors take a scientific strategy, according to IC-system ESD safety co-design. a close description of the to be had IC-level ESD checking out tools is equipped, including a dialogue of the correlation among IC-level and system-level ESD trying out equipment. The IC-level ESD safety layout is established with consultant case experiences that are analyzed with a number of numerical simulations and ESD checking out. the final method for IC-system ESD co-design is gifted as a step by step strategy that contains either ESD checking out and numerical simulations.
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Additional info for System Level ESD Protection
System Level ESD Protection by Vladislav Vashchenko,Mirko Scholz